1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
Priority is claimed on Japanese Patent Application No. 2006-257021, filed Sep. 22, 2006 and Japanese Patent Application No. 2007-217162, filed Aug. 23, 2007, the contents of which are incorporated herein by reference.
2. Description of the Related Art
Semiconductor devices are known in which an n-type diffusion layer, a gate dielectric film, and a gate electrode are formed on a surface of a semiconductor substrate. FIG. 16 is a schematic cross-sectional view showing a cross-sectional structure of a conventional semiconductor device provided with a gate electrode embedded in a trench. In a semiconductor device 101 shown in FIG. 16, a transistor structure T is formed between a pair of trench isolation sections 102. Specifically, an n-type diffusion layer 104 having a source region and a drain region is formed on a surface of a semiconductor substrate 103 having a p-type well layer 103a and a channel doped layer 103b. A trench 105 is formed in the semiconductor substrate 103 and the n-type diffusion layer 104. The source region and the drain region of the n-type diffusion layer 104 are separated by the trench 105. A gate dielectric film 106 is formed on an inner surface of the trench 105 as well as the n-type diffusion layer 104 and the trench isolation sections 102. A gate electrode 107 is embedded in the trench 105 through the gate dielectric film 106. Thus, the gate electrode 107 is formed between the source region and the drain region of the n-type diffusion layer 104 through the gate dielectric film 106. Electrodes 108 and 109 are respectively formed on the source region and the drain region. A silicon oxide film 110 is formed on the gate dielectric film 106. The electrodes 108 and 109 and the gate electrode 107 are embedded in the silicon oxide film 110.
In the semiconductor device 101 shown in FIG. 16, since the gate electrode 107 is embedded in the trench 105, an effective channel length may be controlled in accordance with the depth of the trench, and a higher threshold voltage Vth may be achieved in comparison with that of a conventional planar-type semiconductor device.
In terms of such a trench-embedded semiconductor device, Japanese Unexamined Patent Application, First Publication No. H04-306881 discloses an insulated gate semiconductor device which includes one conductive-type (i.e., p-type (or n-type)) semiconductor substrate, a trench provided in the semiconductor substrate, a gate dielectric film in which the thickness thereof at a bottom surface portion of the trench is smaller than that at a side portion of the trench, a gate electrode provided in the trench through the gate dielectric film, another conductive-type (i.e., n-type (or p-type)) low concentration diffusion layer provided in the semiconductor substrate adjacent to the trench so as to be deeper than the trench, and the other conductive-type (i.e., n-type (or p-type)) high concentration diffusion layer provided in the low concentration diffusion layer adjacent to the gate electrode so as to be shallower than the trench.
In a single electronic tunnel element disclosed in Japanese Unexamined Patent Application, First Publication No. H08-306904, a U-shaped trench is formed in a silicon fine line, the thickness of an oxide film becomes uneven as a result of thermal oxidation because the oxidation rate in the vicinity of a bottom central portion of the U-shaped trench, to which a stress is applied, is less than that in the vicinity of a sidewall of the trench, a gate electrode is formed on the oxide film and a positive gate voltage is applied thereto, thereby electrons are accumulated in the bottom central portion of the U-shaped trench where the oxide film is thin, and a tunnel barrier is formed in the vicinity of the sidewall of the trench where the oxide film is thick.
However, it is difficult to achieve a desired threshold voltage Vth even in such a trench embedded semiconductor device when a wiring is further miniaturized.
On the other hand, a semiconductor device 201 as shown in FIG. 17 has been proposed in which a gate electrode 207 is embedded in a trench 205 through a gate dielectric film 206, and the shape of the trench 205 is formed so that the cross section of an upper portion 205a is rectangular and the cross section of a lower portion 205b is substantially round. Components as shown in FIG. 17 identical to those as shown in FIG. 16 are denoted by the same reference symbols as those of FIG. 16 and their descriptions are omitted. Hereinafter, the semiconductor device 201 as shown in FIG. 17 is referred to as a round-bottom type. The round-bottom type semiconductor device is disclosed, for example, in a literature entitled “S-RCAT (Sphere-shaped-Recess-Channel-Array-Transistor) Technology for 70 nm DRAM feature size and beyond”, J. Y. Kim et al., 2005 Symposium on VLSI Technology Digest of Technical Papers, 2005, pp. 34-35. In accordance with the semiconductor device disclosed in this literature, an effective channel length may be longer than that of a conventional trench-embedded transistor by processing a lower portion of a trench in which a gate electrode is embedded such that its cross section is formed in a round shape. Accordingly, a desired threshold voltage may be achieved even when the transistor is miniaturized. Since the bottom of the trench has a bend portion, an electric field received from the gate electrode may increase in this portion and a sub-threshold factor may decrease, and thus there is an advantage in that it is possible to increase an ON current, i.e., a current flowing through the transistor during the transistor is turned on.
However, in the conventional round-bottom type semiconductor device 201 as shown in FIG. 17, a boundary portion of the upper portion 205a and the lower portion 205b of the trench 205 have a shape of a ridge line protruding to an inner side of the trench 205 at an acute angle. As a result, an electric field is concentrated to the gate dielectric film 206 of the boundary portion, thereby increasing leakage. Accordingly, reliability of the gate dielectric film 206 is lowered.